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Atari Mega Archive 1
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Atari Mega Archive - Volume 1.iso
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tos206up.zoo
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tos206up.txt
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1993-02-02
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525 lines
TOS 2.06 Installation Instructions for 1040ST (V2.0)
Introduction:
This document contains a procedure for installing TOS 2.06 EPROMs into a
1040ST revision C motherboard. A simple circuit consisting of 3 TTL ICs
wire and patience is all that is required. The total cost of the upgrade
will be the cost of the TOS 2.06 EPROMs ($60) plus $1 for the TTL chips.
The OS upgrade should work on other STs as well but this upgrade has only
been implemented on a revision C motherboard of a 1040ST (~1986 vintage).
This upgrade requires some careful soldering so don't try it unless you
have had some PC board soldering experience (don't use a soldering gun!).
I would like to thank all who responded to my questions on notes for their
help. Without the help, I would have had a slim chance of getting this
thing to work.
I would like to suggest that anyone who wants TOS 2.06 to buy it from
Codehead Technologies: (213)-386-5735 They send along a nice manual
and a great utilities disk.
Background:
Most 520ST and all 1040ST computers were shipped with 6 ROMs that contained
TOS (The Operating System). These ROMs are mapped into the address space
0xFC0000 to 0xFEFFFF. This is a 192K byte space. Each ROM holds 32K
bytes. TOS 2.06 is larger than 192K for extra features and bug fixes so
the address space had to be moved. The address space 0xFF0000 to 0xFFFFFF
is used by I/O ports on the ST so the existing space could not just be
increased.
The new address space for TOS 2.06 is 0xE00000 to 0xE3FFFF. I might add
that previous versions of TOS may have been here also but I went from TOS
1.0 to TOS 2.06 so I can't say for sure. Also, instead of putting TOS
2.06 into 8 32K byte ROMs it was placed into two 128K byte EPROMs. One
part is called EVEN (supplies the high 8-bits) the other part is called
ODD (supplies the low 8-bits).
When the 68000 comes out of the reset state, it reads the first 8 bytes
in its address space (0,1,2,3,4,5,6,7). From this data it gets an initial
value for the supervisor stack pointer and the initial value for the
program counter. What the 520ST and 1040ST do (via the GLUE chip) is to
remap addresses 0 through 7 to 0xFC0000 to 0xFC0007. The ROMs are
programmed to have the start address in these locations. TOS 1.0 had the
value 0xFC0020 while TOS 2.06 has the address 0xE00030.
In 520ST and 1040ST computers, the address space 0xE00000 to 0xEFFFFF is
not used or decoded. If a memory cycle is attempted in this range the
data bus will time out and an bus error will result.
The requirements to get TOS 2.06 to work in a 1040ST are as follows:
1. Decode the address range 0xE00000 to 0xE3FFFF and have the TOS 2.06
ROMs drive their data when addressed.
2. Generate DTACK for accesses to TOS 2.06 space.
3. Map the address range 0->7 to 0xE00000->0xE00007.
4. Mechanically connect the EPROMs and decoder logic to the motherboard.
The address range can be decoded with the high 4-bits of the address bus
(A23->A20) to decode the address range 0xE00000 to 0xEFFFFF. This will
work fine because nothing else is in the range 0xE40000 to 0xEFFFFF.
The DTACK signal in the ST is an open collector (wire OR) type bus. This
means that any device that wants to assert DTACK may only do so with an
open collector type interface. This interface basically is one in which
the driver can either drive the line to GROUND or not drive the line at all.
This is different than normal TTL which will drive outputs to GROUND or +5
(in reality 0.4 to 3.8V). The DTACK line has a pull up resistor on it
which will bring the line high if none of the devices on the bus are
driving it low. The DTACK signal can be derived from the decoder logic
but must be buffered with an open collector buffer.
The GLUE chip decodes the 0->7 address range and the range 0xFC0000 to
0xFCFFFF and asserts the signal ROM2 when either of these two ranges are
addressed. The interface can use this fact and OR in the ROM2 signal with
the 0xE????? space to enable TOS 2.06 ROMs. This way the boot up sequence
will be as follows:
1. 68K will read addresses 0->7 which will cause the ROM2 signal from
GLUE to be asserted.
2. Data will be read from locations 0xE00000 through 0xE00007.
3. The 68K will then jump to address 0xE00030 and begin executing code.
4. At this point the ROM2 signal will never be asserted again and the
TOS 2.06 decoder logic will do the work.
The TOS 2.06 EPROMs are a super set of the TOS 1.0 parts. This means that
nearly all of the pins of the new parts can be plugged into the sockets
of the old parts. All of the signals needed for the decoder are available
off of the GLUE chip. Therefore the 3 TTL chips will be placed near the
GLUE chip by glueing them to the motherboard with their pins bent up.
Before you attempt this upgrade make sure that you have enough room between
the two ROM sockets to place the 32-pin parts into the sockets. On the
Rev C mother board there is no problem. The TOS 2.06 chips will have pins
1,2,31 and 32 hanging out over the end of the socket. Basically if there
is more than a quarter inch between U4 and U7 you are set.
Step by Step Instructions:
Please read through the remaining instructions before starting to
determine if this upgrade is something you want to attempt. There are
two main steps. The first step is the construction and testing of the
address space decoder and DTACK logic. The second step is the insertion
of the new ROMs into the system. Before you start you will need a
disk with a program on it to read address 0xE00000. This program will
be used to determine if the decoder and DTACK generator are working.
Before the circuit is implemented the program will generate a bus error
and display bombs on the screen. After the circuit is implemented the
program should just read the value 0xFFFF if you do a 16-bit read.
main()
{
unsigned int *ptr=(unsigned int *)0xE00000;
printf("Value read was 0x%04x\n",*ptr);
}
Step 1 (Implement the Address decoder and DTACK Generator).
The schematic below (I hate ASCII schematics more than you do) shows
the address decoder and DTACK logic. The circuit has 10 signals
that connect directly up to the GLUE chip and 3 signals that connect
directly to the TOS 2.06 ROMs. The GLUE signals are on the left and
the TOS 2.06 EPROM signals are on the right.
(19,XX) ROM2_>--------------------------+ +--------+-----+--------+
| | Chip | +5V | Ground |
74F138 | +--------+-----+--------+
+--------------+ | | 74F138 | 16 | 8 |
(11,52) A23>---|a0(1) q0(15)|o- | | 74F08 | 14 | 7 |
(10,51) A22>---|a1(2) q1(14)|o- | | 74F244 | 20 | 10 |
(09,50) A21>---|a2(3) q2(13)|o- | +--------+-----+--------+
| q3(12)|o- | _______
(12,06) AS_>--o|e1(4) q4(11)|o- | \ \ 74F08
(08,48) A20>--o|e2(5) q5(10)|o- +--o\a(1) \
(55,09) R/W_>---|e3(6) q6(9)|o- ) y(3))o--------> CE_
| q7(7)|o---*-----o/b(2) /
+--------------+ | /______/
|
74F244 |
+-------------+ |
| oe(1)|o---+
(31,10) DTACK_<---|y0(18) i0(2)|--+
| | |
+-------------+ |
|
GROUND
+5V
| ____
+--|4 \ 74F08
| 6 )-------